1. Field of the Invention
The present invention provides a semiconductor device and a fabricating method thereof. More particularly, the present invention provides a semiconductor device with a pocket implant or halo implant technology and a fabricating method thereof.
2. Descriptions of the Related Art
With the evolution of semiconductor manufacturing technologies, semiconductor devices have gradually become smaller with higher densities. However, semiconductor devices with smaller sizes unfortunately are prone to the short channel effect.
Pocket implant or halo implant technology is an approach that is commonly used to improve the short channel effect. FIG. 1A depicts a top view of a conventional semiconductor device 1, while FIG. 1B depicts a schematic cross-sectional view of the conventional semiconductor device 1 taken along a reference line 14. The semiconductor device 1 comprises a substrate 10, a gate structure 11, a source area 12, and a drain area 13. The gate structure 11 comprises a dielectric layer 11a and a gate electrode 11b. According to the conventional pocket implant or halo implant technology, a pocket implant process is applied to the semiconductor device 1 from four directions 10a, 10b, 10c, and 10d. First, ion implantation conditions are set and angles for ion implantations are fixed. Afterwards, via the same photomask, the pocket implant process begins from one of the four directions 10a, 10b, 10c, and 10d (e.g., the direction 10a). The substrate 10 is then rotated horizontally by 90° so that the pocket implant process is applied from a next direction (e.g., the direction 10c), etc. The pocket process proceeds until all the four directions have been applied. Here, the pocket implant process is applied in the directions 10c and 10d for the gate electrode 11b of the semiconductor device 1 and applied in the directions 10a and 10b for a gate electrode (not shown) of another semiconductor device perpendicular to the gate electrode 11b. 
As can be known from FIG. 1B, after the pocket implant process is applied to the semiconductor device 1 in the directions 10c and 10d, pocket implant areas 15, 16 are formed at the inner edges of the source area 12 and the drain area 13 respectively. The pocket implant areas 15, 16 can reduce the transverse electric field between the source area 12 and the substrate 10, as well as the transverse electric field between the drain area 13 and the substrate 10, thereby, improving the short channel effect.
However, as semiconductor manufacturing technologies advance into the nanometer (nm) generation (i.e., generations of 100 nm and below), the problem of device mismatch derived from the pocket implant process applied to the semiconductor device becomes more prevalent. Usually, a compromise can be made between the short channel effect and the device mismatch by adjusting the ion implant dose, the ion implant energy, or the thermal process or by adopting a co-implant process. Nevertheless, as the manufacturing processes advance to increasingly smaller device sizes (e.g., 40 nm and below), the effect thus achieved is very limited.
In view of this, it is important to provide a solution that can provide a compromise between the short channel effect and the device mismatch as manufacturing processes become increasingly smaller (e.g., 40 nm and below).